1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a circuit used in such a device for adjusting the potential level of input/output (I/O) lines for connecting common data buses to bit lines in a memory cell array.
2. Description of the Prior Art
A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in array form, a plurality pairs of bit lines and a plurality of word lines, these bit and word lines being connected to the memory cells. A row decoder and a column decoder for selecting a predetermined memory cell are disposed adjacently to the memory cell array. Further included in the memory device are I/O lines for transferring data read out of and written into the selected memory cell and a plurality of sense amplifiers each amplifying a potential difference between the corresponding bit line pair. The I/O lines are connected through a corresponding one of the selection switches to one of the sense amplifiers. The I/O lines are further connected to common data buses which are in turn coupled via a buffer circuit and an I/O line selecting circuit to an input/output pad provided on the periphery of a semiconductor chip.
In general, for the purpose of improving a data read operation speed, such techniques are applied so that the I/O lines include two wirings in a pair forming a complementary relationship in potential level. A small potential difference appears between the pair of wirings in response to read-out data and the absolute potential value of each I/O line being close to a power supply voltage. In order to set the potential difference appearing between the wiring pair to have a small amplitude, a precharging circuit is provided for supplying the I/O line pair from the power supply voltage during read operation. The precharging circuit includes two transfer gates each coupled between the power terminal and the corresponding one of the I/O lines and turned ON during read operation.
The precharging circuit thus supplies the power voltage to the I/O lines during read operation. On the other hand, the sense amplifier, which is coupled to the I/O lines via the corresponding selection switch, responds to the stored data of the selected memory cell appearing the bit line pair and is intended to raise one of the I/O lines to the high level (the power voltage) and the other of them up to the low level (a ground voltage). Since, however, the driving capability of one sense amplifier is smaller than the driving capability of the precharging circuit, the other I/O line does not drop down to the grounding potential, but is lowered only by about 5% below the power voltage. Thus, the potential difference appearing between the I/O lines becomes small, so that a set-up time for reading out next data is shortened. The data read operation is thereby performed at a high speed.
Recent semiconductor memory devices have been equipped with the so-called fast page mode of operation in which a random read access operation is continuously performed a plurality times on a plurality of memory cells coupled to one word line selected by a row address. In the fast page mode of operation, after reading of data stored in one memory cell, a read operation on another memory cell is carried out by updating only a column address without applying a row address. In other words, such an operation is repeated a plurality of times so that after reading one data in response to the content of the column address, the column address is updated to another content to couple another bit line pair, i.e. another sense amplifier, to the I/O lines via the corresponding selection switch, data stored in the memory cell corresponding to the other content of the column line being thereby read out.
However, during the period from the read of one data to the read of the next data, i.e., during the transition period of the sense amplifier to be coupled to the I/O lines being changed by the selection switch, the column decoder often activates simultaneously a plurality of the selection switches due to the deviation in changing timing of the column address or the like, resulting in the so-called multiselecting state of the selection switches. The I/O lines is thereby driven simultaneously by a plurality of sense amplifiers. For this reason, the potential difference between the I/O lines is broadened, and in the worst case one of the I/O lines is lowered to a potential level that is lower than one half of the power voltage. As a result, the data read operation speed is lowered. More importantly the data stored in the memory cell may be destroyed.